Design of Efficient Reversible Binary Comparator
نویسندگان
چکیده
منابع مشابه
Design and Optimization of n-bit Reversible Binary Comparator
Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is design...
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quantum circuits are promising choices for future quantum computing technology, since the multiple-valued quantum system is more compact than the corresponding binary quantum system. Grover's quantum search algorithm requires a sub-circuit called oracle, which takes a set of inputs and gives an output stating whether a given search condition on the inputs is satisfied or not. Equality, less-tha...
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Modern digital circuit designing is now focussing on the reversible circuits. It aims towards the designing of low power loss circuits in the area of nanotechnology, quantum computing, optical computing, signal processing etc. This paper presents an optimized two-bit binary comparator based on reversible logic using Feynman, Toffoli, TR, URG and BJN gates. Optimization of the comparator circuit...
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Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...
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Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...
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ژورنال
عنوان ژورنال: Procedia Engineering
سال: 2012
ISSN: 1877-7058
DOI: 10.1016/j.proeng.2012.01.943